Today's central processing unit (CPU) architectures often implement a single tier of memory management implemented in a memory management unit (MMU) of the CPU. The MMU can be part of the CPU. The MMU utilizes a translation cache often referred to as a translation lookaside buffer (TLB), backed by storage referred to as a page table (PT), and a hardware or software device for populating the TLB on demand from the PT. The MMU can also include logic to check access permissions, test fault conditions, and if necessary generate a synchronous page fault, which results in the execution by the CPU of a handler routine referred to as a page fault handler (PFH).